1. Field of the Invention
The present invention relates to an integrated circuit for targeted bitlength manipulation of a transmitter for serial data transmission. More particularly, the present invention relates to an integrated circuit that is particularly suitable for integrated digital logic units.
2. Description of the Prior Art
As serial bus systems are further improved, increases in data transfer rate or maximum wire length may cause distortion of bit lengths in wires which have a progressively more serious effect on quality of a transmission. Particularly in serial data transmission through optical waveguides, as bit rate rose, transmission medium had to be improved correspondingly.
Equalization means on a receiver and complex integrated circuit for restoring a serial datastream are known from a number of sources including German Patent Nos. DE 33 35 418 A1 or DE 198 55 707 A1. A further possibility for improving transmission quality consists in pre-emphasizing a serial data signal in a transmitter. To ensure a most finely adjusted temporal differentiation possible in the pre-emphasis, high partial bit resolution is necessary. A disadvantage of this, however, is that in digital circuits, higher partial bit resolution requires a higher clock speed in order to generate a bit. All components of the integrated circuit used to generate a partial bit must possess a same rapid internal switching capability.
A receiving device for bit-serial asynchronous data transmission is taught by German Patent No. DE 33 35 418 A1. A measurement device which includes digital logic elements and is connected to a delay line is used to detect a received data signal in temporal relation to a local clock of a receiver. A gating device, known as a priority encoder, strips control signals accordingly, so that data bits are called in their correct phase in each case. For this purpose, phase position of the local clock must be brought into a desired temporal position relative to the received clock using a clock control unit. However, the clock control unit described here must be supported by high-performance signal runtimes to logic gates that are used in the clock control unit. These high demands in terms of signal runtimes cannot generally be satisfied in field programmable gate arrays (FPGAs).
German Patent No. DE 198 55 707 A1 teaches a device for generating a low-distortion receiving signal for high bit-rate transmissions. The receiving signal is analyzed in a receiver, wherein a pre-emphasis device in the receiver generates bits of an outgoing datastream based on a result of the analysis. Means for analyzing the receiving signal is extraordinarily complicated because weighting of each bit is done on a basis of a series of measurement points. Monitors receive the measurement points and control the pre-emphasis device based on results of the measurement. The means for providing the low-distortion receiving signal also requires extremely sophisticated and rapid components which analyze the receiving signal and address the pre-emphasis device based on results of the analysis. Such a device for providing a low-distortion receiving signal can only be integrated in field programmable gate arrays (FPGAs), if at all, with application of an extremely complex circuit design. A further disadvantage that applies to all pre-emphasis devices in receivers is that after a certain degree of distortion, the receiving signal is no longer recognizable and plausible pre-emphasis is therefore no longer possible.
In xe2x80x9cHigh Speed Communication with RS-422/485xe2x80x9d, Elektronik Industrie [Electronics Industry], 9 2001, pre-emphasis of a data signal in a transmitter is described. In the temporal pre-emphasis, a system clock must be an integral multiple of a bit clock (data rate). It follows that a smallest partial bit length is directly dependent on the system clock, which means that when very short partial bits are essential to allow precise adjustment of bit lengths to a transmission path, a fast system clock is needed.
A settable clock generation within an FPGA is described in xe2x80x9cVirtex-II Platform FPGA Handbookxe2x80x9d, Xilinx, Dec. 6, 2000. The clock generation is capable of providing multiple timing signals at one clock rate in different phase positions. With the settable clock generation, it is possible to measure up to 4 timing signals having a same clock rate but in different phase positions. However, a set phase position of a respective timing signal can only be initialized before the device is put into operation, i. e. it must be preset and cannot be altered during operation. A phase position that is controllable during operation can only be changed by stages, which means that it is not possible to manipulate a bit over a longer temporal range.
The object of the present invention is to provide a simple and inexpensive circuit design for targeted bitlength manipulation for serial transmission of data. The integrated circuit generates the datastream to be transmitted in which bits for output are subjected to a targeted bitlength manipulation process. The integrated circuit is realized by means of highly integrated field programmable gate arrays (FPGAs) with digital logic units, wherein requirements of an internal system clock are not very stringent, and with a result that the integrated circuit may be provided with internal runtimes of the FPGAs.
The serial datastream to be transmitted is entered serially into a history register with a bit clock associated with a data rate and having a scanning clock of the data rate. A gating device analyzes the datastream to be outputted with reference to bit statuses in the history register. The gating device in turn indicates which individual partial bits are to be transmitted to a wire or a signaling converterxe2x80x94not further described herexe2x80x94as a serial data stream with a system clock at a speed that is a multiple of a prior clock. Rules regarding a number of partial bits by which each bit is to be manipulated are stored as values in the gating device, or are provided by another device, which is not further described here. Multiple partial bit register chains are provided, wherein each register chain is clocked relative to a next partial bit register chain with a phase shifted system clock.
In a simplest case, the integrated circuit according to the present invention has two partial bit register chains, wherein a first is clocked using the system clock, and a second is clocked with an inverse of the system clock thereby achieving a phase shift of 180 degrees. Both partial bit register chains are loaded with a parallel data vector determined by the gating unit before each bit is outputted. Using an offset arrangement of partial bits in the partial bit register chains, the partial bits are always outputted according to half periodic duration of the system clock. In this case, offset arrangement is understood to mean that, for example, in the first partial bit register chain, starting with bit 0, every second partial bit thereafter in the first partial bit register chain is preloaded in parallel, and in the second partial bit register chain, starting with bit 1, every second partial bit thereafter in the second partial bit register chain is preloaded in parallel. A gate as a joining link of the serial output from the first partial bit register chain with the serial output from the second partial bit register chain generates the pre-emphasized serial datastream to be outputted. The gate is an only internal circuit component which must have a rapid response capability and minimal runtime differentials for an output of a 0 status as compared with an output of a 1 status.
1: History register
2: Serial datastream Ser_Data
3: CLK_B, scanning clock for serial datastream
4: History bit vector
5: Control unit
6: CLK_TB, system clock
7: Partial bit vector TB0 to TB7
8: Bit generator
9: Generated datastream Ser_Data_Out
10: Load control signal for accepting partial bit vector
11: Multiplexer
12a-h: Register
13: Multiplexer
14a-d: Register of the first register chain
15a-d: Register of the second register chain
16: Serial output of the first register chain
17: Serial output of the second register chain
18: Gate
19: CLK_TBxe2x80x94180, 180 degree phase-inverted system clock
20: Bit length
21: First 1 shortening
22: Second 1 shortening
23: Start time